1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor. In particular, the present invention relates to a semiconductor device having a bit line that serves as a source region and a drain region and is buried in a semiconductor substrate.
2. Description of the Related Art
In recent years, non-volatile memory semiconductor devices wherein data can be overwritten are widely used. In the technical field of such non-volatile memories, technological developments are being made to miniaturize memory cells for high storage capacity. For example, there are metal oxide nitride oxide silicon (MONOS)-type Flash memories and silicon oxide nitride oxide silicon (SONOS)-type Flash memories in which electric charge is stored in an oxide/nitride/oxide (ONO) film. Furthermore, flash memories have been developed that have two or more charge storage regions in one transistor for the purpose of increasing storage capacity. For example, U.S. Pat. No. 6,011,725 discloses a transistor having two charge storage regions between a gate electrode and a semiconductor substrate. This transistor interchanges the source and drain and is symmetrically operated. In this manner, a structure that does not differentiate between the source region and the drain region may be provided. Furthermore, bit lines serve as the source and drain regions and are buried in the semiconductor substrate. In this way, the memory cells can be miniaturized.
A conventional manufacturing method is explained referring to FIGS. 1(a) through 1(d). In FIG. 1(a), a tunnel oxide film 12 (silicon oxide film) and a trap layer 14 (silicon nitride film) are formed on a P-type semiconductor substrate 10 in this order. A photoresist 40 is applied and an opening is formed using an ordinary exposure technique. In FIG. 1(b), arsenic, for example, is ion-implanted with the photoresist 40 as a mask, and an N-type high concentration diffusion region 22 is formed. In FIG. 1(c), a pocket implantation is performed with the same photoresist 40 as the mask, and pocket implantation regions 28 are formed. The pocket implantation is a method of forming P-type regions with a higher concentration than the P-type semiconductor substrate 10 next to both sides of the high concentration diffusion region 22, by, for example, boron implantation at an angle (such as 15°) to the vertical direction of the semiconductor substrate 10. In this manner, the junction profile near the high concentration diffusion region 22 on the semiconductor substrate 10 surface can be steepened. Thus, when a voltage is applied between the source region and the drain region (bit line 30a), the electric field near the high concentration diffusion region 22 can be enlarged.
In FIG. 1(d), the photoresist 40 is removed and a top oxide film 16 (silicon oxide film) is formed. In this way, an ONO film 18 composed of the tunnel oxide film 12, the trap layer 14, and the top oxide film 16 is formed. A polycrystalline silicon film is formed and a predetermined area is removed using an ordinary exposure technique and an etching technique. Thus, a word line 32 that serves as a gate electrode is formed. Subsequently, the flash memory is completed by formation of an interlayer insulating film 34, formation of a wiring layer 36, and formation of a protective film 38.
The semiconductor substrate 10 between the bit lines 30a functions as a channel, electric charge is stored in the ONO film between the channel and the word line 32, and this flash memory functions as a non-volatile memory. The storage of electric charge in the ONO film 18 is performed by applying a high electric field between the source region and the drain region (namely, between the bit lines 30a), and implanting electrons that have become high energy into the trap layer 14 within the ONO film 18. In addition, favorable writing characteristics can be obtained because the electric field near the high concentration diffusion region 22 on the surface of the semiconductor substrate 10 can be enlarged by the performance of pocket implantation.
In addition, data is erased by applying a negative voltage to the gate electrode (namely, word line 32) and generating Fowler-Nordheim (F-N) tunneling or Band to Band Tunneling current in the tunnel oxide film 12. The charge storage regions can be formed in two locations between the bit lines 30a under the word line 32, by interchanging the source region and the drain region with each other.
Because the bit line 30a is formed from the diffusion region, the resistance thereof is higher than the resistance of metal. As a result, the programming and erasing characteristics become poor. Therefore, the bit line 30a is connected to the wiring layer 36 by contact holes formed on the interlayer insulating film 34 every time a plurality of word lines 32 is crossed. In order to miniaturize the memory cells, the bit line 30a is required to have a low resistance and it is necessary to reduce the number of contact holes connecting with the wiring layer 36.
Conventionally, in order to lower the resistance of a bit line 30a for the purpose of miniaturizing the memory cells, it is preferable to increase the energy and increase the dosage of the ion implantation that forms the bit line 30a. Furthermore, it is preferable to shorten the distance between the bit lines 30a. However, because the bit line 30a serves as the source region and the drain region, the source region and the drain region are formed with a high energy and high dosage. Therefore, in writing data and the like, if a high voltage is applied between the source region and the drain region (namely, between the bit lines 30a), junction current flows between the source region and the drain region reducing the source-drain breakdown voltage. In addition, reading characteristics for reading data may also be degraded. These issues interfere with the miniaturization of the memory cells.